International Journal of Advanced Innovative Technology in Engineering (IJAITE)

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CMOS Design Of Tree Multiplier Using Low Power And Area Efficient Full Adder

MS. S. A. DRAVYEKAR

Abstract :

The beginning of Digital electronic with the of vacuum tubes. But implementation of larger engines became economically and practically infeasible. As electrons have higher mobility than holes, NMOS was preferred later so micro processors chip used NMOS-only logic, with higher speed relative to the PMOS logic. But later, NMOS-only logic started suffering from the same problem, power consumption. In case of CMOS, addition of a single input become a greater the device count by 2 and thus maximum the propagation delay. New logic styles were developed to minimize the propagation delay and chip area. In this paper present high-speed and low-power full-adder cells proposed with an alternative internal logic structure and pass-transistor logic styles that lead to have a less power-delay product (PDP). Wallace high-speed multipliers use full adders and half adders in their moderation phase. Half adders do not reduce the number of partial product bits. Therefore, reduce the number of half adders used in a multiplier reduction will minimum the complexity. A modification to the Wallace reductions gives guarantees that the delay is the same as for the conventional Wallace reduction

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